Minutes, IBIS Quality Committee

09 Sep 2008

11-12 AM EST (8-9 AM PST)

ROLL CALL
  Adam Tambone
  Anders Ekholm, Ericsson
  Barry Katz, SiSoft
  Benny Lazer
  Benjamin P Silva
  Bob Cox, Micron
* Bob Ross, Teraspeed Consulting Group
  Brian Arsenault
  David Banas, Xilinx
* Eckhard Lenski, Nokia Siemens Networks
  Eric Brock
* Guan Tao, Huawei Technologies
  Gregory R Edlund
  Hazem Hegazy
  Huang Chunxing, Huawei Technologies
  John Figueroa
  John Angulo, Mentor Graphics
  Katja Koller, Nokia Siemens Networks
  Kevin Fisher
  Kim Helliwell, LSI Logic
* Lance Wang, IOMethodology
  Lynne Green
* Mike LaBonte, Cisco Systems
  Mike Mayer, SiSoft
* Moshiul Haque, Micron Technology
* Pavani Jella, TI
  Peter LaFlamme
  Randy Wolff, Micron Technology
  Radovan Vuletic, Qimonda
  Robert Haller, Enterasys
  Roy Leventhal, Leventhal Design & Communications
  Sherif Hammad, Mentor Graphics
  Todd Westerhoff, SiSoft
  Tom Dagostino, Teraspeed Consulting Group
  Kazuyoshi Shoji, Hitachi
  Sadahiro Nonoyama

Everyone in attendance marked by *

NOTE: "AR" = Action Required.

-----------------------MINUTES ---------------------------
Mike LaBonte conducted the meeting.

Call for patent disclosure:

- No one declared a patent.

AR Review:

- none

New items:

Mike reviewed where we are with respect to document versions and checks reviewed.

Continued review of the IBIS Quality Specification:

5.4.1.	{LEVEL 2}  V-T table endpoints consistent with I-V tables
- Level 2 is correct for this.
- Moshiul: IBISCHK flags this.
- We decied to delete this check.

5.4.2.	{LEVEL 3}  V-T tables look reasonable
- Bob: "Excess points" not clear
- Moshiul: V-T length relates to clock frequency
  - Mike: At one time simulators had problems with this, but no more
  - Moshiul: At least one still has trouble
- Mike: Is it OK to have 4 checks in one?
  - Yes
- Moshiul: The time window must be set to allow for slow case settling
  - But this can look too long for the fast case
  - The slow start time tends to start later even if fast has no lead time
- Bob: Remove the right amount for each corner, but same across waveforms
  - Fast corner has different amount of delay removed than slow
  - Remove same amount for all rising and another amount for all Falling
- Mike: May be difficult to adjust typ/min/max separately
  - s2ibis produces a combined table
  - In a spreadsheet the columns have to be shifted in fixed amounts
- Bob: The amount removed for Rising and Falling should be the same
  - Otherwise there may be duty cycle distortion
  - Wea are assuming the SPICE stimulus is consistent
  - IBIS works OK if time shift is not important
- Mike: How much lead time is too much?
  - Should be less than 50% of total time
  - Bob: 50% is arbitrary
  - Moshiul: We have no specific number:
    - Avoid DC mismatch
    - Dead time is removed
    - Prefer max to start before typ, which is before min
    - Pavani: Agree
  - Mike: Simulator has to make choices when told to reverse half way up an edge
  - Bob: Vendors are complying with a spec like DDR
    - That may also limit how much leading delay is allowed

AR: Moshiul rewrite 5.4.5 to describe leading waveform delay requirements

Mike is unavailable Sep 16:
- Our next meeting will be in 2 weeks.

Next meeting:

23 Sep 2008 11-12 AM EST (8-9 AM PST)

Meeting ended at 12:10 PM Eastern Time.
